MD_HX711 Library 1.0
Library to interface HX711 Weigh Scales Module
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Hardware Control

Sampling Rate

The HX711 can sample at 10 samples per second (SPS or Hz) or 80Hz, set by the RATE pin on the IC.

Some module boards have a jumper on the reverse side of the board to set the rate, as shown below. Connecting RATE to 1 (Vcc) sets 80Hz and 0 (GND) is 10Hz.


Reset and Power Down Sequence

When power is first applied, the power on circuitry will reset the IC.

The CLK output from the processor is also used to reset the HX711 IC. CLK should LOW by the processor unless clocking during a read cycle (see below).

When CLK is

  • LOW, the HX711 is in normal working mode.
  • changed from LOW to HIGH and stays HIGH for longer than 60μs, the HX711 is powered down. It remains in this state while the signal remains high.
  • changed from HIGH to LOW, the HX711 resets and restarts normal working mode.

Following a reset the hardware defaults to Channel A input, gain 128.


Data Read and Gain Control

CLK is set by the processor, DAT is read by the processor. These two digital signals make up the serial interface to the HX711.

The data is read as 24 bits clocked out, one bit per clock cycle, from the HX711. Additional clock transitions (+1 to +3) are used to set the mode for the next read cycle according to the handshaking sequence below.

  • When an ADC reading is not available, DAT is set HIGH by the HX711. CLK is held LOW by the processor.
  • When DAT goes to LOW, the next ADC conversion can be read by the processor.
  • The processor sends 25 to 27 positive (transition LOW to HIGH) CLK pulses to shift the data out through DAT one bit per clock pulse, starting with the MSB, until all 24 data bits are shifted out.
  • The HX711 will then hold DAT HIGH for the remainder of the clock pulses.
  • Channel and Gain selection for the next read is controlled by the number of additional CLK pulses (+1 to +3) send to the HX711, for a total of 25 to 27 clock pulses as shown in the table below.
Clock Pulses Input Channel Gain
25 A 128
26 B 32
27 A 64

Fewer than 25 and more than 27 clock pulses in one communication cycle will cause a serial communication error requiring a HX711 reset.